2024
[FPGA’24] Jiahui Xu and Lana Josipović. Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing. In Proceedings of the 32nd ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, pages 188–98, Monterey, CA, March 2024.
[FPGA’24] Ayatallah Elakhras, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. In Proceedings of the 32nd ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, pages 44–54, Monterey, CA, March 2024.
2023
[ICCAD’23] Jiahui Xu and Lana Josipović. Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. In Proceedings of the Intl. Conference on Computer-Aided Design, pages 1–9, San Francisco, CA, Nov 2023.
[ICCAD’23] Hanyu Wang, Carmine Rizzi, and Lana Josipović. MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization. In Proceedings of the Intl. Conference on Computer-Aided Design, pages 1–9, San Francisco, CA, Nov 2023. Best Paper Award Nominee.
[IWLS’23] Jiahui Xu and Lana Josipović. Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. In Proceedings of the Intl. Workshop on Logic Synthesis, pages 179–87, Lausanne, Jun 2023.
[IWLS’23] Hanyu Wang, Carmine Rizzi, and Lana Josipović. MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization. In Proceedings of the Intl. Workshop on Logic Synthesis, pages 28–36, Lausanne, Jun 2023.
[TRETS’23] Lana Josipović, Axel Marmet, Andrea Guerrieri, and Paolo Ienne. Resource sharing in dataflow circuits. ACM Transactions on Reconfigurable Technology and Systems. 16(4):1–27, September 2023.
[TRETS’23] Jianyi Cheng, Lana Josipović, John Wickerson, and George A. Constantinides. Parallelising Control Flow in Dynamic-Scheduling High-Level Synthesis. ACM Transactions on Reconfigurable Technology and Systems. 16(4):1–32, September 2023.
[DAC’23] Carmine Rizzi, Andrea Guerrieri, and Lana Josipović. An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits. In Proceedings of the 60th Design Automation Conference, pages 1–6, San Francisco, CA, July 2023.
[FPGA’23] Jiahui Xu, Emmet Murphy, Jordi Cortadella, and Lana Josipović. Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. In Proceedings of the 31st ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, pages 27–37, Monterey, CA, February 2023.
[FPGA’23] Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. In Proceedings of the 31st ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, pages 39–45, Monterey, CA, February 2023.
2022
[FPT’22] Jiantao Liu, Carmine Rizzi, and Lana Josipović. Load-Store Queue Sizing for Efficient Dataflow Circuits. In Proceedings of the 21st International Conference on Field-Programmable Technology, pages 1–9, Hong Kong, December 2022.
[FPL’22] Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, and Lana Josipović. A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. In Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, pages 375–83, Belfast, August 2022.
[FPL’22] Ayatallah Elakhras, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. In Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, pages 253–61, Belfast, August 2022. Best Paper Award Nominee.
[FPL’22] Jianyi Cheng, Lana Josipović, John Wickerson, and George A. Constantinides. Dynamic Inter-Block Scheduling for HLS. In Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, pages 243–52, Belfast, August 2022. Best Paper Award Nominee.
[TCAD’22] Lana Josipović, Andrea Guerrieri, and Paolo Ienne. From C/C++ code to high-performance dataflow circuits. IEEE Transactions on Computer-Aided Design, 41(7):2142–55, July 2022.
[FCCM’22] Lana Josipović, Axel Marmet, Andrea Guerrieri, and Paolo Ienne. Resource sharing in dataflow circuits. In Proceedings of the 30th IEEE Symposium on Field-Programmable Custom Computing Machines, pages 1–9, New York, NY, May 2022. Best Paper Award Nominee.
2021
[TRETS’21] Lana Josipović, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. Buffer placement and sizing for high-performance dataflow circuits. ACM Transactions on Reconfigurable Technology and Systems. 15(1):1–32, November 2021.
[CASM’21] Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Synthesizing general-purpose code into dynamically scheduled circuits. IEEE Circuits and Systems Magazine, 21(2):97–118, May 2021.
[TCAD’21] Jianyi Cheng, Lana Josipović, George A. Constantinides, Paolo Ienne, and John Wickerson. DASS: Combining dynamic and static scheduling in high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. March 2021.
[FPGA’21] Lana Josipović, Axel Marmet, Andrea Guerrieri, and Paolo Ienne. Resource sharing in dataflow circuits. In Proceedings of the 29th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, page 226, February 2021. Abstract only.
2020
[FPGA’20] Lana Josipović, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. Buffer placement and sizing for high-performance dataflow circuits. In Proceedings of the 28th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, pages 186–96, Seaside, Calif., February 2020. Best Paper Award.
[FPGA’20] Jianyi Cheng, Lana Josipović, George A. Constantinides, Paolo Ienne, and John Wickerson. Combining dynamic & static scheduling in high-level synthesis. In Proceedings of the 28th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays , pages 288–98, Seaside, Calif., February 2020.
[FPGA’20] Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Dynamatic: From C/C++ to dynamically scheduled circuits. In Proceedings of the 28th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, pages 1–10, Seaside, Calif., February 2020.
2019
[FPT’19] Lana Josipović, Atri Bhattacharyya, Andrea Guerrieri, and Paolo Ienne. Shrink it or shed it! Minimize the use of LSQs in dataflow designs. In Proceedings of the IEEE Intl. Conference on Field Programmable Technology, pages 197–205, Tianjin, China, December 2019.
[IWLS’19] Lana Josipović, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. Performance optimization of dataflow circuits. In Proceedings of the Intl. Workshop on Logic Synthesis, pages 146–53, Lausanne, June 2019.
[FPGA’19] Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Speculative dataflow circuits. In Proceedings of the 27th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, pages 162–71, Monterey, Calif., February 2019.
2018
[FPGA’18] Lana Josipović, Radhika Ghosal, and Paolo Ienne. Dynamically scheduled high-level synthesis. In Proceedings of the 26th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, pages 127–36, Monterey, Calif., February 2018. Best Paper Award Nominee.
2017
[ACSSC’17] Lana Josipović, Philip Brisk, and Paolo Ienne. From C to elastic circuits. In Proceedings of the 51st Annual Asilomar Conference on Signals, Systems, and Computers, pages 121–25, Pacific Grove, Calif., October 2017.
[CASES’17] Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. In Proceedings of the Intl. Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Seoul, Korea, October 2017. See ACM TECS paper below. Best Paper Award Nominee.
[TECS’17] Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. ACM Transactions on Embedded Computing Systems, 16(5s):125:1–125:19, September 2017.
[FCCM’17] Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. In Proceedings of the 25th IEEE Symposium on Field-Programmable Custom Computing Machines, page 134, Napa, Calif., April 2017.
2016
[FPT’16] Lana Josipović, Nithin George, and Paolo Ienne. Enriching C-based high-level synthesis with parallel pattern templates. In Proceedings of the 26th IEEE Intl. Conference on Field Programmable Technology, pages 177–80, Xi’an, China, December 2016.