DYNAMO

Digital Systems and Design Automation

2023
  • Jiahui Xu, Emmet Murphy, Jordi Cortadella, and Lana Josipović. Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. In Proceedings of the 31st ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’23), Monterey, CA, February 2023, to appear.
2022
  • Jiantao Liu, Carmine Rizzi, and Lana Josipović. Load-Store Queue Sizing for Efficient Dataflow Circuits. In Proceedings of the 21st International Conference on Field-Programmable Technology (FPT’22), Hong Kong, December 2022, to appear.
  • Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, and Lana Josipović. A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. In Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications (FPL’22), pages 375–83, Belfast, August 2022.
  • Ayatallah Elakhras, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. In Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications (FPL’22), pages 253–61, Belfast, August 2022. Best Paper Award Nominee.
  • Jianyi Cheng, Lana Josipović, John Wickerson, and George A. Constantinides. Dynamic Inter-Block Scheduling for HLS. In Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications (FPL’22), pages 243–52, Belfast, August 2022. Best Paper Award Nominee.
  • Lana Josipović, Andrea Guerrieri, and Paolo Ienne. From C/C++ code to high-performance dataflow circuits. IEEE Transactions on Computer-Aided Design (TCAD), 41(7):2142–55, July 2022.
  • Lana Josipović, Axel Marmet, Andrea Guerrieri, and Paolo Ienne. Resource sharing in dataflow circuits. In Proceedings of the 30th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’22), pages 1–9, New York, NY, May 2022. Best Paper Award Nominee.
2021
2020
2019
  • Lana Josipović, Atri Bhattacharyya, Andrea Guerrieri, and Paolo Ienne. Shrink it or shed it! Minimize the use of LSQs in dataflow designs. In Proceedings of the IEEE Intl. Conference on Field Programmable Technology (FPT’19), pages 197–205, Tianjin, China, December 2019.
  • Lana Josipović, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. Performance optimization of dataflow circuits. In Proceedings of the Intl. Workshop on Logic Synthesis (IWLS’19), pages 146–53, Lausanne, June 2019.
  • Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Speculative dataflow circuits. In Proceedings of the 27th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’19), pages 162–71, Monterey, Calif., February 2019.
2018
  • Lana Josipović, Radhika Ghosal, and Paolo Ienne. Dynamically scheduled high-level synthesis. In Proceedings of the 26th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’18), pages 127–36, Monterey, Calif., February 2018. Best Paper Award Nominee.
2017
  • Lana Josipović, Philip Brisk, and Paolo Ienne. From C to elastic circuits. In Proceedings of the 51st Annual Asilomar Conference on Signals, Systems, and Computers, pages 121–25, Pacific Grove, Calif., October 2017.
  • Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. In Proceedings of the Intl. Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES’17), Seoul, Korea, October 2017. See ACM TECS paper below. Best Paper Award Nominee.
  • Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. ACM Transactions on Embedded Computing Systems (TECS’17), 16(5s):125:1–125:19, September 2017.
  • Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. In Proceedings of the 25th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’17), page 134, Napa, Calif., April 2017.
2016