Specialized hardware accelerators (e.g., ASICs and FPGAs) offer a promising solution to our growing computational demands through their high performance and energy efficiency. However, their widespread adoption is limited by the complexity, cost, and time required to design and optimize hardware. DYNAMO’s research focuses on advancing compilation, synthesis, and verification techniques to make the design of conventional and emerging hardware systems more accessible, efficient, and reliable. Our research spans several areas of computer science and electrical engineering, including compilers, formal methods, electronic design automation, digital circuit design, and computer architecture.
Our research outputs are publicly available on GitHub or on dedicated websites (e.g., Dynamatic), and our papers are usually accompanied by reproducible artifacts on Zenodo. Please check our publications page for links associated with each paper. Our research is generously supported by the Swiss National Science Foundation, Horizon Europe, Innosuisse, ETH Future Computing Laboratory, Cadence Design Systems, Google, AMD, Jane Street, and imec.
Research Areas
1. Hardware Compilation and Synthesis
From high-level programs to efficient hardware implementations
Our research advances compiler and synthesis techniques that automatically translate high-level programs into efficient hardware implementations, with the goal of making specialized hardware easier to design and program. We investigate high-level synthesis methods that expose and exploit parallelism beyond conventional approaches. One of our main projects is Dynamatic, an open-source high-level synthesis compiler that generates dataflow circuits which dynamically adapt to runtime conditions, providing substantial performance improvements and supporting capabilities beyond standard HLS.
Selected publications: FPGA’18, FPGA’24.
2. Hardware Design Space Exploration
Finding efficient hardware designs through automated exploration
We investigate techniques that systematically explore hardware design alternatives to best meet application requirements, as well as methods to adapt applications to the target hardware architecture. Our research combines performance and resourse estimation, predictive modeling, and automated optimization to efficiently navigate large design spaces. We investigate hardware-software co-design techniques that jointly optimize application mappings and architectural decisions for high performance and energy efficiency.
Selected publications: ICCAD’24, MICRO’26.
3. Logic Synthesis and Circuit Optimization
Optimizing digital circuits for performance, area, and efficiency
We develop algorithms and design automation techniques for optimizing digital circuits and mapping them onto diverse technologies. Our research tackles logic optimization, technology mapping, placement, and routing to improve performance, area, energy efficiency, and implementation time. We are particularly interested in synthesis methods that exploit information across different abstraction levels and integrate implementation information into the optimization process.
Selected publications: ICCAD’23, FPL’24.
4. Hardware Verification
Ensuring correctness and security in automated hardware design
We investigate formal methods and verification techniques to reason about correctness and security of hardware designs and the transformations used to create them. We explore equivalence checking, model checking, invariant generation, and correct-by-construction design to ensure that hardware optimizations and transformations preserve the required behavior. We also investigate security properties, such as timing side channels, and develop methods to integrate security guarantees into automated hardware design.
Selected publications: FPGA’23, ASPLOS’25.
5. Energy-Efficient Computing
Reducing energy consumption through design automation
We investigate software compilation and hardware synthesis techniques that improve the energy efficiency of computing systems. Our research tackles power modeling and estimation, switching activity reduction, and energy-aware workload-architecture co-optimization. By incorporating energy considerations across different hardware design stages, from architectural decisions to circuit-level optimization, we aim to reduce energy consumption while balancing area, performance, and implementation complexity.
Selected publications: FPL’24, ICCAD’26.
6. Design Automation for Emerging Technologies
Enabling new computing technologies through compilation and synthesis
We explore compiler and electronic design automation techniques for emerging computing technologies and architectures. We investigate methods for programming, mapping, and designing unconventional systems, including new reconfigurable devices, processing-in- and near-memory architectures, and 3D circuits, with the goal of making them more accessible and efficient.
Selected publications: ISCA’25, CASES’26.